Efficient CNN Deployment on FPGA: A Dual Strategy for Feature and Weight Storage Optimization

In the traditionallayer-by-layer computation model, the deployment of classic Convolutional Neural Network (CNN) models on resource-constrained Field-Programmable Gate Array (FPGA) platforms faces frequent off-chip memory access issues, resulting in significant inference delays. To address this challenge, this paper proposes two solutions targeting layers with larger feature sizes: a feature row cache pipeline streaming mechanism based on an inter-layer handshake strategy and an on-chip weight storage optimization scheme based on inter-layer fusion and intra-layer chunking. To validate the feasibility of these solutions, we implement hardware acceleration experiments for the YOLOv4-Tiny model (layers 1–12) on Xilinx XCZU19EG, and explored the potential application of the core idea presented in this paper for processing layers with a larger number of weight parameters.