Polymer-Free and Dry Patterning of Wafer-Scale Two-Dimensional Semiconductors via van der Waals Delamination

Two-dimensional (2D) semiconductors have attracted a considerable amount of interest as channel materials for future transistors. Patterning of 2D semiconductors is crucial for separating continuous monolayers into independent units. However, the state-of-the-art 2D patterning process is largely based on photolithography and high-energy plasma/RIE etching, leading to unavoidable residues and degraded device uniformity, which remains a critical challenge for the practical application of 2D electronics. Here, we report a polymer-free and dry-patterning technique for wafer-scale 2D semiconductors. Upon lamination of a three-dimensional Au stamp onto monolayer MoS₂ and then it being peeled away, the Au-contacted region will be effectively removed while the noncontacted regions are successfully left on its growth substrate. The fabricated MoS₂ transistors exhibit a 100% device yield, increased carrier mobility, and much reduced device-to-device variation, compared to those of conventional wet-patterned devices. Our work provides a simple and rapid dry-patterning technique for 2D wafers, which is important for the lab-to-fab transition.