Durin: CPU-FPGA Heterogeneous Platform for Scalable Low-Dimensional Data Clustering

Reconfigurable hardware accelerators, known for their high performance and power efficiency, have yet to be fully leveraged for clustering low-dimensional data at realistic scales. In this work, we identify and address two hurdles for accelerating this important class of applications: the overhead of implementing indexing data structures in hardware, and the PCIe bottleneck when the data capacity spills over from accelerator memory to host storage. We overcome these hurdles for the first time with Durin, a CPU-FPGA heterogeneous system with a hardware-software codesigned index structure, which minimizes the hardware resource overhead of high-performance neighbor search. It also minimizes PCIe overhead by facilitating asynchronous acceleration of distance calculation, and block floating-point compression. We show that a desktop computer with Durin implemented on a mid-range Alveo U50 FPGA can outperform a 32-thread Xeon server by almost 20× , with an order of magnitude power efficiency improvements. Furthermore, Durin outperforms even the best-case projection of a conventional standalone accelerator design, which implements the entirety of the clustering algorithm in the FPGA and its High Bandwidth Memory (HBM), by 2×.