A Novel Trench-Gate MOSFET with Sidewall N+ Region and Low Switching Loss

In this paper, a SiC trench MOSFET with source contact integrated on the inclined trench side wall on {0-33-8} face (VS-MOS) is proposed and investigated by TCAD simulations. The presented VS-MOS overcomes the disadvantage of the increased cell pitch introduced by the inclined trench sidewall. Meanwhile, VS-MOS demonstrates a low specific on-resistance of 1.14 mΩ.cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a maximum gate oxide electric field <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(E_{ox,m})$</tex> of 3.45 MV/cm at blocking voltage at 1200V. Furthermore, a novel structure featuring P-base-covered trench corner is presented based on the VS-MOS structure (VSB-MOS). The <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$E_{ox,m}$</tex> is significantly decreased to 2.72 MV/cm. Dynamic characteristics are also studied, the switching loss for the VS-MOS is 2.659 mJ/cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> which is reduced by 28.6% compared to the V-MOS. The gate-to-drain charge for the VSB-MOS is 166.56 nC/cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>, which is reduced by 21.04% as a comparison with V-MOS. The cell pitch of the VS-MOS and VSB-MOS is reduced by 26.58% and 28.15% than V-MOS, respectively. The fabrication process of the proposed structures is more competitive than the V-MOS both technically and economically.