Optimization of JFET Doping in the Fabrication of 4H-SiC MOSFETs

The effect of doping concentration of JFET region on the static and dynamic characteristics of 1200 V 4H-SiC power MOSFET is studied. The simulated results show that the increasing concentration of JFET region would reduce the onstate resistance, but the threshold voltage would become lower and the turn-on and turn-down losses would become larger. After trade-off, the proper JFET doping has been chosen and 1200 V SiC MOSFETs are fabricated with and without JFET implantation. It is found that the on-state resistance of the device with JFET implantation has reduced by about 37.6 %. Both the two devices have a high breakdown voltage over 1500 V. In addition, after JFET implantation, the gate-drain capacitance has risen slightly. In general, the proper JFET implantation has improved the electrical performances of SiC VD-MOSFETs.