6-Inch GaN/Si CMOS 1P2M Monolithic Heterogeneous Process and Platformed Devices

To solve problems of parasitic effects in interconnects, low reliability, and three-dimensional stress associated with 3D heterogeneous and stacking of small chips, the complete process and model research of a 6-inch 20V GaN/Si CMOS 1P2M/(111) Si monolithic heterogeneous integration in the paper is put forward at the first time. Innovations have been made in high-quality patterned selective epitaxy of GaN, compatibility of GaN/Si-based P-well CMOS processes, and platformed device design. This work has overcome several engineering challenges associated with the process integration of 6-inch Si CMOS IC and GaN IC chips, leading to the development of key devices such as (1) Si PMOS with a threshold voltage/current drive (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</inf>/I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</inf> (forward)) of -0.7V, 2.5 mA/mm; (2) high-performance bulk silicon PN diodes with a forward voltage (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</inf>) of about 0.72~0.79 V; (3) PNP and NPN silicon bipolar devices with β of approximately 260 and 300, respectively; (4) AlGaN/GaN HEMTs with V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</inf>/I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</inf> (forward) of -3V, 300–500 mA/mm. A prototype platform for heterogeneous integration processes, including Si CMOS and GaN processes, has been established.