Effects of JFET Widths on Static and Dynamic Characteristics in Silicon Carbide MOSFETs

The static and switching performances of Silicon Carbide (SiC) MOSFETs with different JFET widths are investigated by test and simulation in this paper. The device with larger JFET width exhibits preferable output and transfer characteristics due to better current spread capability of the accumulation layer, but worse blocking and switching characteristics because of the exceeded 4 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\times 10^{6}\ \mathrm{V}/\text{cm}$</tex> electric field strength in oxide layer and larger gate to drain capacitance. This paper proves that the JFET width should be designed in a compromise based on actual electrical parameters, but should better not exceed 3 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mu\mathrm{m}$</tex>, providing a theoretical supplement for futural designment.

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Publication Details

Published
2024-11-18
DOI
https://doi.org/10.1109/sslchinaifws64644.2024.10835363
Primary Topic
Silicon Carbide Semiconductor Technologies
Type
article
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Effects of JFET Widths on Static and Dynamic Characteristics in Silicon Carbide MOSFETs

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10 links
Silicon Carbide Semiconductor Technologies
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Effects of JFET Widths on Static and Dynamic Characteristics in Silicon Carbide MOSFETs

Ling Sang, Xinyu Li, Xiping Niu, Zelong Li, Rui Jin, Yawei He
article en

Abstract

The static and switching performances of Silicon Carbide (SiC) MOSFETs with different JFET widths are investigated by test and simulation in this paper. The device with larger JFET width exhibits preferable output and transfer characteristics due to better current spread capability of the accumulation layer, but worse blocking and switching characteristics because of the exceeded 4 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\times 10^{6}\ \mathrm{V}/\text{cm}$</tex> electric field strength in oxide layer and larger gate to drain capacitance. This paper proves that the JFET width should be designed in a compromise based on actual electrical parameters, but should better not exceed 3 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mu\mathrm{m}$</tex>, providing a theoretical supplement for futural designment.

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Silicon Carbide Semiconductor Technologies
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