Design and Fabrication of a Novel 1200V 4H-SiC Trench Bottom P Shielding MOSFET with Assisted Deep P Implantation by the Side

In this paper, a silicon carbide (SiC) trench bottom p shielding (P+SLD) MOSFET with assisted deep-implanted P+ (DP) region by the side (PGP-TMOS) is designed and fabricated experimentally. The P+SLD is grounded by connecting periodically to the P+ region in the direction which is perpendicular to the gate trench. The connecting is realized by using optimized layout design without the need for additional process exploration. The P+SLD together with the DP region modulates the electric field at the corner of the trench, thereby providing improved protection for the gate oxide. To demonstrate the effect of the DP region, a SiC trench bottom P+SLD MOSFET without DP region (GP-TMOS) is designed. The cell pitch of the GP-TMOS is greatly reduced due to the absence of the DP region. Numerical 2D-simulation has been carried out to study the characteristics of these two structures. Simulation results show that the peak electric field in the gate oxide <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(E_{\text{ox},\text{peak}})$</tex> for the PGP-TMOS and GP-TMOS at the drain voltage of 1200V is 1.70MV/cm and 2.22MV/cm, respectively. In addition, compared with the GP-TMOS, the Baliga figure of merit (BFOM) of the PGP-TMOS is improved by 22.90%. Test results of the experimental samples of the PGP-TMOS show that the breakdown voltage (BV) is 1400 V and the on-state resistance <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(R_{\text{on}})$</tex> is 49.7 mΩ. Furthermore, the impact of some key parameters on the PGP -TMOS structure is discussed, which provides guidance for subsequent optimization.