Design and Demonstration of a Novel 4H-SiC Full-P Encapsulated Trench MOSFET with Three-Level Protection Multi-Step Gate Trench Structure

In this paper, a novel 4H-SiC full-P encapsulated trench MOSFET with three-level protection multi-step gate trench structure is proposed and discussed with detailed parametric design. The proposed structure realizes the three-level protection of gate oxide in the blocked state by virtue of the P buried layer, the P shield layer, and the multi-step gate trench. The effects of CSL layer concentration, P shield layer thickness, and the width and depth of the multi-step gate trench on the maximum electric field strength of gate oxide <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(E_{\text{ox},\max})$</tex> and the on-resistance <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(R_{\text{on},\text{sp}})$</tex> are discussed. The proposed structure achieves an excellent compromise between <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$E_{\text{ox},\max}$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$R_{\text{on},\text{sp}}$</tex>. Simulation results show that the proposed new structure reduces <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$E_{\text{ox},\max}$</tex> by 12.3% without affecting the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$R_{\text{on},\text{sp}}$</tex>. In addition, a fabrication process with feasibility of the novel structure is proposed and demonstrated with customized N-P-N sandwich epitaxial wafers.