Approximate squaring circuits for error-resilient applications

Most approximation computing research focuses on arithmetic operations like binary multiplication, division, and addition. Squaring, another fundamental arithmetic operation, is commonly required. Allowing small errors can improve circuit performance, which is useful for error-tolerant applications. The recursive squaring approach, which employs approximate multipliers and squarers, reduces redundant computations, power consumption, delay, and area in computing circuits. This paper proposes a 4-bit approximate squarer P1, which is implemented in the recursive squaring methodology. In the comparison between the exact and approximate squares employed by the proposed squarer P1, it was observed that area decreased by 79.20%, power by 58.55%, and delay by 50.81%. Error metrics like error rate, MRED, and MNED are also analyzed and compared with exact squarer. The behaviour of the proposed configurations is tested using the amplitude modulation application. The designs are synthesized using Cadence Genus with a 90nm technology library.