“Ship Lock” Thermal Design of Power Chip Packaging and Its Effects on Thermal Performance and Reliability Based on Dimensional Parameters

The study devises a SiC thermal management design inspired by the “lock gate” concept and employing Ag/Cu sintering technology. It adopts the multi-stage idea of lock gates, attaching a copper “heat pool” beneath the Ag/Cu sintering layer of power chips to rapidly absorb heat, thereby reducing heat accumulation within the chip. The design also incorporates Cu pillar or hollow pipe structures to further transfer heat around the chip, with additional copper pillars or heat pool structures at the end of the next-level pipes to convey heat deeper into the substrate, eventually dissipating it to the underside of the substrate. This approach effectively lowers both the chip junction temperature and the chip-to-ambient thermal resistance. Moreover, the multi-stage thermal design facilitates structural optimizations, such as reducing via holes, which in turn decreases parasitic parameters of the device, benefiting its switching speed and operational frequency. For a 5W power chip, the junction temperature dropped from 559.646°C to 362.760°C, marking a maximum reduction of 35.18%. Comparisons between two “lock gate” schemes and a single “heat pool” design revealed chip junction temperatures of 468.588°C, 456.983°C, and 492.397°C respectively, validating that the “lock gate” design enhances substrate thermal conductivity beyond that achievable with just a “heat pool” design. During experiments and simulations, the thermal performance of copper heat pools under interconnect materials like Ag/Cu sintered material, conductive silver adhesive, and IMC solder Sn-2Ag-0.5Cu-0.05Ni was investigated. The impact of interconnect layers on chip junction temperature was found to be minimal at only 2°C. It was also discovered that once the thermal conductivity of interconnect layers exceeds 50–60 W/(m.K), their influence on chip junction temperature gradually diminishes. Building upon this, the relationship between sinter layer width and copper heat pool dimensions on thermal performance and reliability was explored. Achieving 100% sinter layer coverage on the substrate significantly reduced the chip junction temperature to 315.578°C, demonstrating the effectiveness of extensive silver sinter layers in lowering chip temperatures. Furthermore, the influence of heat pipe dimensions on thermal performance was verified, with extending the heat pipes to the substrate edge reducing chip junction temperature to 397.271°C. Although this is less effective than large-area silver sinter layers, it still leads to a substantial decrease in temperature. By introducing a toothed copper pillar structure beneath the heat pool, the junction temperature was further reduced to 362.760°C. The optimized design reduced the package's junction temperature and thermal resistance by 35.18% and 57.44%, respectively, compared to the initial design. Testing confirmed that this design improves device reliability, enhancing lifespan by 24.9%, reducing equivalent plastic strain by an order of magnitude (down by 75.83%), and decreasing overall strain by 14.5%. Through optimizing the sintering process, the chip's push-shear tensile strength reached 22.7 MPa. Using blind vias and buried vias to replace through vias predictably reduces the parasitic parameters of the package, thereby improving the operating frequency, packaging performance, and reliability of power chips.