An Ultra-Low-Jitter Fast-Hopping Fractional-N PLL With LC DTC and Hybrid-Proportional Paths

This work presents an ultra-low-jitter fractional-N PLL capable of wideband fast hopping. There is an analog proportional path and a digital proportional/integral path in the PLL. The PLL is digital-path-dominant during settling and analog-path-dominant after settles; therefore, the fast-lock characteristic of the digital PLLs and the low-jitter characteristic of the analog PLLs are achieved. The frequency switching algorithm does not rely on the linearity of DCO’s tuning curve, nor rely on the hopping step between the previously locked frequency and the target frequency. The frequency detection is based on a high-speed counter, which uses the quadruple timing margin selection and can operate up to 20 GHz. The counter is integrated with a feedback clock generator, which is functionally the same as a multi-modulus divider. In addition, this work proposes an LC delay circuit as the coarse digital-to-time converter (DTC), which has better potential than the RC-based counterparts to reduce the phase noise of DTC and thereby reduce the jitter of fractional-N PLLs. The prototype is implemented in 28-nm CMOS process and occupies 0.21-mm2 core area. The measured hopping time is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.52~{\mu }$ </tex-math></inline-formula>s across a 3.5-GHz step with 80-ppm settling accuracy. The measured rms jitter (integrated from 1 kHz to 100 MHz) is 36.8 fs for the integer-N channel, 41.3 fs for the far-integer fractional-N channel, and 61.7 fs for the near-integer fractional-N channel. The measured near-integer fractional spur is -62.4 dBc. The measured power consumption is 34 mW.