Mixed-Dimensional α -In₂Se₃/Ge Junction Field-Effect Transistors With High Electron Mobility and Low Subthreshold Swing

In recent years, traditional CMOS platforms have encountered common issues when the channel thickness is reduced to 5 nm. In this study, Type-I junction field-effect transistors (JFETs) were fabricated based on mixed-dimensional <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\alpha $ </tex-math></inline-formula>-In2Se3/Ge heterojunctions. As a result, the device exhibited n-type transfer behavior with depletion-mode characteristics. The current on-/off-ratio reached <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{4}}$ </tex-math></inline-formula> regardless of source-drain voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {ds}}$ </tex-math></inline-formula>). The minimum subthreshold swing (SS) was calculated to be 101 mV/dec at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {ds}} =1$ </tex-math></inline-formula> V. Furthermore, at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {ds}} =1.5$ </tex-math></inline-formula> V, the on-state saturation current density and maximum electron mobility reached <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.107~\mu $ </tex-math></inline-formula> A/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>m and 87.5 cm2/V <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\cdot $ </tex-math></inline-formula> s, respectively. Benefiting from the high-quality heterojunction, the device demonstrated a small threshold voltage shift (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta {V}_{\text {Th}}$ </tex-math></inline-formula>) of 0.45 V, indicating a low interface trap density of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.23\times 10^{{10}}$ </tex-math></inline-formula> cm<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-{2}}$ </tex-math></inline-formula>. Overall, our designed architecture, compatible with Si CMOS technology, is suitable for application in high-speed n-type loaded MOSFET and ferroelectric FETs.