Compact PNP BJT-Based Temperature Sensor and Sub-1-V Bandgap Reference for SoC Applications in 4-nm FinFET
This article presents a dual-function circuit of a temperature sensor and a sub-1-V bandgap reference (BGR) implemented in the 4-nm FinFET CMOS process. The design, based on subthreshold MOS transistors and parasitic PNP bipolar junction transistor (BJT) devices, offers distinct advantages over existing PNP BJT-based sensors and sub-1-V BGRs. As a temperature sensor, it achieves the fastest conversion time of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$7~{\mu }$ </tex-math></inline-formula> s, while consuming a power of only <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$68.5~{\mu }$ </tex-math></inline-formula> W, which results in the lowest energy consumption rate of 0.5 nJ per conversion. In addition, the sensor demonstrates a resolution of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.46~{^{\circ }}$ </tex-math></inline-formula>C and a resolution figure-of-merit (FOM) of 0.106 nJ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\cdot $ </tex-math></inline-formula> K2. It also functions as a low-cost, high-accuracy BGR capable of sub-1-V operation, producing a stable output of 450 mV within a compact 0.0061 mm2 footprint, and featuring an accuracy of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pm 1.1\% (\pm 3\sigma)$ </tex-math></inline-formula> along with an average temperature coefficient (TC) of 33 ppm/°C. Moreover, by supporting both BGR and sensing modes, the design significantly reduces costs by incorporating dual functionalities within a single architecture.
Authors
- Y. Fan (ORCID: https://orcid.org/0000-0001-5914-2765)
- James Ayers (ORCID: https://orcid.org/0000-0001-9801-3384)
- You Li (ORCID: https://orcid.org/0000-0001-6609-4562)
- D. Duarte (ORCID: https://orcid.org/0000-0001-8846-0324)
Institutions
- Intel (United States) (US)
Publication Details
- Journal
- IEEE Journal of Solid-State Circuits
- Published
- 2025-01-16
- DOI
- https://doi.org/10.1109/jssc.2024.3524245
- Citations
- 5
- Primary Topic
- Advancements in Semiconductor Devices and Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 3.65