A 5-MS/s 16-bit Low-Noise and Low-Power Split Sampling SAR ADC With Eased Driving Burden

This article presents a 16-bit 5-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with the proposed split sampling (SS) technique. The SS decouples the sampling and conversion operations of the ADC, effectively addressing the tradeoff among the driving burden of the digital-to-analog converter (DAC), sampling noise, power, and bit-cycling speed. The SS consists of 2 20-pF sampling capacitors and a 1-pF DAC. The sampling capacitors sample the input with low noise and cancel the kT/C noise of the DAC, avoiding the preamplifier saturation issue and easing the noise aliasing. As the sampling capacitors track the input when the DAC is performing bit-cycling, the input driving is eased with the extended tracking time. The small DAC guarantees fast speed and low power. Moreover, statistical residue measurement (SRM) is employed to reduce the preamplifier’s noise and the quantization noise, efficiently improving the signal-to-noise-and-distortion ratio (SNDR) and the bit weight calibration accuracy. The ADC is fabricated in a 180-nm process and occupies an active area of 0.57 mm2. With the SS and SRM, the ADC samples at 5 MS/s and achieves a 93.7-dB SNDR with a 5.31-mW power consumption, yielding a high Schreier-figure-of-merit (FoM) of 180.4 dB.