Scale effects in BEOL compatible ferroelectric field-effect transistor memories with random phase fluctuation

Abstract In this study, we investigate the effects of dimensional scaling on device variation of back-end-of-line (BEOL) compatible ferroelectric field-effect transistor (FeFET) memory with amorphous oxide-semiconductor channel by considering random ferroelectric/dielectric (FE/DE) phase fluctuation. Our study based on TCAD simulation indicates that: (i) For a given FE phase, scaling gate length not only improves memory window (MW) due to the sufficient ferroelectric switching during erase, but also increases MW variation ( σ MW ), which is mainly dominated by high-voltage threshold (HVT) variation induced by erase operation. (ii) For a given device size, reducing FE phase results in decreased MW with increased σ MW . This σ MW degradation could be suppressed at longer gate length due to the weak erase. (iii) For gate width scaling, it has negligible effect on MW but induces the σ MW increase, which could be ascribed to the increased probability of forming DE paths with larger grain-to-channel area ratio. Therefore, although scaling BEOL FeFET device size could increase MW, the increased σ MW due to random FE/DE phase fluctuation may also need to be considered. These findings may provide insights for future FeFET design.