Efficiency Evaluation of a Modified Montgomery Multiplication Systolic Architecture Implemented on an FPGA

This work presents an improved algorithm applied to a systolic architecture when a modular multiplication is synthesized into a Field Programmable Gate Array (FPGA). Here, we proved how this proposed architecture for modular multiplication can be employed in a modular exponentiation process. Modular exponentiation is critical and helps in the performance of algorithms like RSA, Digital Signature, Elliptic Curve, and other cryptographic algorithms. Results obtained show that these improvements in the systolic architecture speed up the performance and reduces also the resources used by the programmable device, specifically when the Montgomery modular multiplication is used. Also, we compare the results of this work with related work published in the literature.