Design and Performance Analysis of a Ge/GaAs/Si-Based DG-JL-TFET for Ultra Low Power Applications

This paper introduces a detailed investigation of the design and performance of a new type of transistor called the Ge/GaAs/Si-based Double-Gate Junctionless Tunnel Field-Effect Transistor (DG-JL-TFET). The transistor is specifically designed for use in ultra-low power applications. The proposed DG-JL-TFET utilizes the distinctive material properties of germanium (Ge), gallium arsenide (GaAs), and silicon (Si) to achieve enhanced electrical performance while minimizing power consumption. This addresses the limitations of current structures, including random doping fluctuations, low current driving capability, and ambipolar behavior. The inquiry utilizes a mathematical and computational methodology to simulate and enhance the device's properties. The work utilizes statistical modeling techniques to investigate the effects of variations in key geometric factors, such as gate length (L<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</inf>), oxide thickness (tox), and channel thickness (tch). Polynomial words are utilized to numerically represent these variables, facilitating a comprehensive investigation of their impact on device performance. For this analysis, the current when the device is not in use is set at a constant value of 9.6 femtoamperes, resulting in a current of 6.7 milliamperes when the device is in use. The construction additionally decreases the threshold voltage to 0.35 V, while achieving a ft value of 744 GHz and a fmax value of 855 GHz. The findings emphasize the capability of the Ge/GaAs/Si-based DG-JL-TFET to provide improved switching efficiency and energy conservation, positioning it as a promising contender for future low-power devices.