A 10 Gb/s MIPI D-PHY Receiver with Auto-skew Calibration Circuit using Random Data

A high-speed receiver including an auto- skew calibration circuit for 10 Gb/s mobile industry processor interface (MIPI) D-PHY is proposed to support data communication of high-performance cameras using four data lanes and one clock lane. The proposed auto-skew calibration circuit, consisting of a delay line and skew control blocks for data and clock, supports skew calibration for predetermined training data while also supporting skew calibration for random data not defined in the MIPI D-PHY. It performs a phase comparison between the clock and the data for skew calibration, which uses only the rising edge of the data instead of the rising and falling edges of the clock as the reference signal. The delay line used in the skew calibration circuit uses a delay cell consisting of three NANDs consuming 1.41 mW at full delay. The proposed MIPI D-PHY receiver including the auto-skew calibration circuit is designed by using a 28-nm CMOS process with a supply voltage of 1.0 V. The proposed MIPI D-PHY receiver circuit receives 2.5 Gb/s of data per data lane for a total of 10 Gb/s of data and consumes 0.4 mW/Gbps/lane. The proposed auto skew calibration circuit improves the data skew from 148 ps to 19 ps and from 230 ps to 18 ps for the predetermined training and random data, respectively.