A 99.93% Peak Current Efficiency Digital-LDO using Single VCO With Dual Frequency Gain Control

The proposed digital low-dropout voltage regulator (DLDO) automatically controls clock frequency based on the difference between the reference and feedback voltage. Enabling adaptive frequency regulation during voltage ringing events, and thus assisting rapid transient response. Unlike prior approaches utilizing two voltage-controlled oscillators (VCOs) to generate frequencies for controlling pass gates, this work employs a single VCO, reducing the need for VCO control voltage pins. The proposed DLDO regulates the output at 1 V from a 1.2 V supply and has been implemented based on a 65 nm CMOS process. The transient time is 782 ns, a power efficiency of 99.93%, and the FOM is 15 fs.