Research on Vector Extension of Instruction Set Architecture
With the development of instruction set architecture, vector extension has become an important way to improve processor performance. The vector instruction set adds support for single instruction multiple data (SIMD) operations by extending the base instruction set, so that the processor can use one instruction to perform the same operation on multiple data elements. The extension of this instruction set greatly improves the parallelism of data processing. It has brought significant system performance improvement for scientific computing, multimedia processors and other fields. With the wide application of vector instructions in various fields, different instruction set architectures have developed their own unique vector instruction sets. This paper surveys the vector instruction set of three architectures: RISC-V, ARM, x86. Analyze the characteristics of three vector instruction sets, and they provide developers with rich parallel processing capabilities to meet the needs of different application scenarios. The purpose of this paper is to study and compare the vector instruction sets of RISC-V, ARM and x86, to provide reference for the selection and optimization of processor architecture.
Authors
- Jiangdong Wang
- Lixin Yu (ORCID: https://orcid.org/0009-0004-8164-914X)
- Zhiyong Qin (ORCID: https://orcid.org/0000-0003-0208-8109)
- Yang Xue (ORCID: https://orcid.org/0000-0002-6814-4428)
- Shi‐Yuan Zhang (ORCID: https://orcid.org/0000-0002-7199-2938)
- Wei Zhuang (ORCID: https://orcid.org/0000-0002-2470-7268)
Institutions
- Beijing Microelectronics Technology Institute (CN)
Publication Details
- Published
- 2024-10-11
- DOI
- https://doi.org/10.1109/cbase64041.2024.10824427
- Primary Topic
- Simulation and Modeling Applications
- Type
- article
- Field-Weighted Citation Impact
- 0.00