Maximizing Cost Performance Ratio Review of Domino Logic Circuits Design Based on FinFETs

Domino logic circuits are preferred for high-speed operation but suffer from high power losses, and the use of FinFET technology can improve the situation and the circuit’s performance. Domino logic circuits, due to their lower noise margin, have a superior performance in comparison to static gate circuits, as this leads to less interference. The domino circuit’s adoption of symmetric bias-independent gate technology, which holds the transistor, inevitably reduces the noise margin as a result of reducing power consumption and delay. In this paper, we evaluate power reduction by collating the numerous existing optimization design methods for domino logic circuits and performing analysis under different modes. These studies provide a reference for FinFET-based optimized domino logic circuit selection.