Deep Neural Network Accelerator: Exploring the Potential of 3D Chiplet Integration

The development of deep neuro networks brings a sharp rise in demands for expeditious convolutional computing operations, but the “memory wall” originated from the intense data transfer, has greatly hindered the performance of deep neural network accelerators. As the integrated circuits have entered the post-Moore's law era, evolving the neural network accelerator by advance semiconductor fabrication technology is no longer available. This paper presents an in-depth analysis of data flow within a fundamental neural processing unit system, examining the impact of 3D integration and chiplet architecture on overcoming the “memory wall” challenge. A versatile neural processing unit architecture, featuring adjustable processing elements and buffer sizes, is developed to evaluate performance improvements induced by 3D chiplet integration. The results prove the feasibility of 3D chiplet integration in performance advancement of neural processing unit from both memory and processing element perspectives, which provides a complete guidance for potential solutions for reducing memory bottlenecks.