Constructing Random QC-LDPC Codes Based on the Relationship between 8-Cycles and Trapping Sets

This paper presents a computer-aided search scheme based on simulated annealing methodology for regular quasi-cyclic low-density parity-check (QC-LDPC) codes, ensuring a minimum girth of at least 8. The approach utilizes the simulated annealing algorithm, leveraging the correlation between cycles and trapping sets, and analyzes their positioning in the Tanner graph to iteratively reduce trapping sets. This process ultimately results in the generation of high-girth QC-LDPC codes. A significant advantage of our method is that it greatly reduces the search time compared to existing approaches. Furthermore, our method generates QC-LDPC codes that demonstrate a diminution in the number of 8-cycles, concurrently achieving a reduction in detrimental trapping sets. Simulation results reveal that our method generates QC-LDPC codes with excellent bit error rate performance.

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Publication Details

Published
2024-10-24
DOI
https://doi.org/10.1109/wcsp62071.2024.10826749
Primary Topic
Error Correcting Code Techniques
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article
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article

Constructing Random QC-LDPC Codes Based on the Relationship between 8-Cycles and Trapping Sets

Defeng Ren, Guohua Zhang, Shuai Lv
Error Correcting Code Techniques
article

Constructing Random QC-LDPC Codes Based on the Relationship between 8-Cycles and Trapping Sets

Defeng Ren, Guohua Zhang, Shuai Lv
article en

Abstract

This paper presents a computer-aided search scheme based on simulated annealing methodology for regular quasi-cyclic low-density parity-check (QC-LDPC) codes, ensuring a minimum girth of at least 8. The approach utilizes the simulated annealing algorithm, leveraging the correlation between cycles and trapping sets, and analyzes their positioning in the Tanner graph to iteratively reduce trapping sets. This process ultimately results in the generation of high-girth QC-LDPC codes. A significant advantage of our method is that it greatly reduces the search time compared to existing approaches. Furthermore, our method generates QC-LDPC codes that demonstrate a diminution in the number of 8-cycles, concurrently achieving a reduction in detrimental trapping sets. Simulation results reveal that our method generates QC-LDPC codes with excellent bit error rate performance.

Xi’an University of Posts and Telecommunications (CN)
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Error Correcting Code Techniques
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