Voice Recognition Acquisition and Storage System using VHDL and the DE1-SoC FPGA

This paper presents the design of a voice acqui-sition and recognition system in VHDL, mainly optimized for FPGA DE1-SoC. The system implements advanced digital signal processing techniques combined with classification through the K-Nearest Neighbors (KNN) algorithm. The system operates at a 320 kHz sampling rate, with a latency of 10 ns and power consumption of 1.2 W. The design enhances precision and noise rejection through the use of Hamming windows and integer-based processing. Future improvements will focus on the implementation of neural networks to replace the KNN algorithm and further increase system accuracy.