Exploratory Approach to Reduce IR Issue in Low Power Test Compression Methodology

Power-aware tests are increasingly critical for both functional operation and manufacturing because of the challenges posed by high power dissipation in various test modes. Excessive test power can lead to multiple issues during manufacturing and field tests, particularly during scan-shift operations, which exhibit high switching activity and potentially excessive IR drop. Reducing IR drop during testing is essential to prevent delay-induced yield loss. To address this, we propose a Design for Testability (DFT)-based approach that controls the number of chains loading scan data at any given time using DFT-inserted registers. The Automation Test Pattern Generation (ATPG) tool automatically configures these registers, generating appropriate control bit values for the test patterns. This approach applies to both stuck-at-fault and dynamic (at-speed) test sets. Identifying the right switching control is challenging, as it must balance coverage and pattern counts. Design-dependent heuristics used for scan switching values affect the Quality of Results (QoR) achieved by the ATPG engine. This paper presents an evaluation framework for structural testing that leverages a Machine Learning-driven (ML) flow to identify switching activity and achieve optimal QoR. With the approach followed, we observed a decreasing trend in the number of instances for which IR drop is more than the threshold of 20% during scan shift. The improvement seen can be presented as the number of instances for which IR drop during the scan shift is violating the threshold of 20% reducing from~1 million instances to 42 and 72 instances on two experimental designs with relatively no impact on the area.