Post-Silicon DV: Simplifying and Accelerating a Complex Debug Journey

Due to tremendous growth in the demand for modern and complex designs, there are various testing and validation methodologies available to enable rapid time-to-market of the SoCs. However, despite that, validation is widely acknowledged as a major bottleneck in SoC design methodology, accounting for an estimated 50% of overall time and resources spent on SoC design validation. Despite a thorough verification process, there are still probabilities of functional failures in the first silicon due to differences between the simulation and tester environment, process variations, and device types. This paper focuses on the pivotal role of Design Verification (DV) methodologies in streamlining the complex post-silicon debug journey. By seamlessly integrating with Automated Test Equipment (ATE) and Application Verification and Validation (AVV) Bench flow, this paper outlines verification methodologies that accelerate functional testing at volume while drastically reducing turnaround time for post-silicon debugs.