An efficient scandump methodology to left shift DFT testing into Gate-level Verification

The rising need for fast, power efficient SoCs have resulted in complex designs and the need for short time to market has resulted in rigorous verification strategies. Safety conscious use cases of these System on Chips (SoCs) such as automotive sector demand a fault free SoC with high redundancy. Various faults, timing issues and functional errors found post placement and routing or in the silicon can prove difficult to be fixed. These issues can be found during Design-for-Testability (DFT) with post placement and routing netlist or post silicon. We explore the possibility of left shift of these methodologies into Design Verification stage and Gate Level Simulations of scandump testing proves to be a valuable candidate for this verification. By using a dedicated memory controller with Low-Power Double Data Rate (LPDDR) memory for storing scan data, the need for an external hardware debugger is eliminated and enables DFT testing to be carried out at Design Verification stage (DV). Identifying clock glitches, data integrity errors and scan chain issues at Gate Level Simulation (GLS) allows fixing of design issues easier and cost effective compared to post-silicon Engineering Change Order (ECO).