Interoperable SoC Framework for PCIe Design Verification Challenges

The growing complexities in the Peripheral Component Interconnect (PCIe) designs with each new generation brings in even more challenges in PCIe verification. There is an increasing trend of ASIC re-spins, coupled with the industry demands for lesser Time to Market (TTM) makes it inevitable to take actions to close the verification gap as much as possible, as quickly as possible. This must be done incrementally with better solutions and the proposal takes steps to mitigate some of the PCIe design and verification challenges. The PCIe verification effort has increased 90-fold from PCIe 5.0 to PCIe 6.0. The interoperability issues have an estimated 6-fold increase from PCIe 3.0 to PCIe 6.0. This paper provides a comprehensive solution with a System Verilog (SV) and Universal Verification Methodology (UVM) based framework entailing a PCIe design IP and Verification IP (VIP), that provides a standard scalable environment. The framework facilitates quicker and easy integration of IP into a subsystem or SoC, solves the interoperability issues, employs methods like Register Abstraction Layer (RAL) based configuration APIs for reuse and configurability. The framework facilitates faster testbench bring up, with first PCIe linkup and first test pass time brought down by 75% per PCIe IP. This helps in achieving quick, quality pre-silicon verification sign-off boosting post-silicon confidence.