Resolving Care-Bit Correlations Using Clock Gates
Automotive applications have very stringent test requirements, including testing while in-field. The decompressor structure in the scan compression suffers from congestion whenever care-bits in a pattern are clustered in same or adjacent cycles. In this paper we present a novel technique to reduce the correlation between subsequent decompressor states. We introduce dummy or buffer states dynamically at selected scan slices. The solution is generic and independent of any scan compression or logic BIST architecture. We also present the design techniques and share results on benchmark circuits.
Authors
- Prateek Singh (ORCID: https://orcid.org/0000-0002-6574-302X)
- Sandeep Kumar Jain (ORCID: https://orcid.org/0000-0003-1247-1806)
- Sanjeev Kumar Pathak
Publication Details
- Published
- 2024-11-12
- DOI
- https://doi.org/10.1109/wintechcon61988.2024.10838147
- Primary Topic
- Embedded Systems Design Techniques
- Type
- article
- Field-Weighted Citation Impact
- 0.00