Cell-Aware ATPG under Electrical Voltage Stress

Conventional testing methods struggle to ensure high quality in sub-10nm Integrated Circuits (ICs) for critical applications in automotive and healthcare. Shrinking geometries lead to two issues: (1) many defects within and between cells remain undetected by test patterns, and (2) fault grading becomes unreliable due to smaller defect signatures mimicking process variations. Cell-aware test (CAT) improves defect coverage, but some latent defects, especially in the lowest metal layers, remain hidden even under stress. These defects require elevated voltage stress for activation. Such latent defects require elevated voltage stress and the capability to generate and grade patterns based on fault activation for the defects to pop out and be detectable. In this paper, CAT pattern generation flow is oriented to target cell-aware test by generating and grading the right set of patterns based on fault activation under elevated voltage stress. This paper presents a novel and comprehensive approach for testing cell-aware defects under elevated voltage stress. It highlights the quality and reliability of the pattern grading under elevated Process, Voltage, and Temperature (PVT) corners in industrial designs to showcase increased performance, pattern count, and test coverage. The focus is on producing an optimal set of stress patterns that helps achieve maximum coverage within a practical timeframe. In summary, we observed an increase in defect coverage of ~24.02% for 100 patterns across 9 designs under elevated voltage stress test compared to conventional IDDQ tests. The probability of defect occurrence would increase multi-fold in complex designs especially with multi-bit cells. This novel approach can be leveraged for such convoluted multi-bit cell designs.