Novel Leakage Reduction Technique for Ultra-Low Power Advanced FinFET Technology Node Design

This paper presents an effective leakage reduction technique for ultra-low power circuits, designed using advanced technology node. The technique involves identification of devices having high sub-threshold leakage in a design, and appropriately biasing them to optimize it. The biasing scheme is used to vary the terminal voltages of the devices and obtain the lowest leakage operating point, at which the sum of drain to substrate leakage and drain to source leakage is minimal. In addition, the transient performance specifications are met, and there is no increase in overall macro area. The technique is shown to be effective beyond well-known methods like stacking, for varied designs. Around 70% reduction in post layout leakage is achieved, using the novel technique discussed in this work.