Impact of Impurities on Leakage Current Induced by High-Energy Density Pulsed Laser Annealing in Si Diodes
Pulsed laser annealing (PLA) offers significant advantages over conventional thermal processes for semiconductor device fabrication. Notably, it can provide ultrafast (~ns) and high-temperature (>1000 °C) profiles. When the maximum temperature exceeds the melting point, a solid-to-liquid phase transition occurs, followed immediately by rapid recrystallization. Power devices, such as insulated-gate bipolar transistors (IGBTs), require micrometer-sized junctions that are used as injection layers (collectors) on the back side of processed wafers. PLA, when used at high laser energy densities, proved to be an attractive technique for this application because it provides the appropriate thermal budget while avoiding damage to the front side of the device. However, this unique annealing mechanism raises questions about dopant diffusion and residual defects in the recrystallized region and just below it. Indeed, these energy densities (ED) have been shown to promote the incorporation of complex impurities from the surface and the creation of defects at the liquid/solid interface. This article reports on the impact of laser annealing at high energy densities (ranging from 1.7 to 8.0 J/cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>) and multipulse modes (between 1 and 10) on leakage current and capacitance-deep level transient spectroscopy (C-DLTS) measurements using Schottky and p–n diodes. Our results suggest that the solubility of vacancies in silicon is fixed by the maximum temperature reached and the ED. Increasing the number of laser pulses enables one to reach the maximum vacancy concentration and promote diffusion toward the surface. Concurrently, the diffusion of complex impurities into the melted region enables coupling between the two defect types, creating trap centers responsible for degrading the leakage current.
Authors
- Éric Imbernon
- Antonino La Magna (ORCID: https://orcid.org/0000-0002-4087-5210)
- M. Italia
- F. Cristiano (ORCID: https://orcid.org/0000-0003-1839-9972)
- Richard Daubriac (ORCID: https://orcid.org/0000-0001-9641-9719)
- Richard Monflier
- Simona Boninelli (ORCID: https://orcid.org/0000-0002-7359-3586)
- Toshiyuki Tabata (ORCID: https://orcid.org/0000-0003-4923-5663)
- E. Bedel Pereira
- Louis Thuries (ORCID: https://orcid.org/0000-0001-5814-1656)
- Fulvio Mazzamuto (ORCID: https://orcid.org/0000-0002-6056-951X)
- François Olivier
- Mahmoud Haned
Institutions
- Centre National de la Recherche Scientifique (FR)
- Université Toulouse III - Paul Sabatier (FR)
- Université Fédérale de Toulouse Midi-Pyrénées (FR)
- Laboratoire d'Analyse et d'Architecture des Systèmes (FR)
- Laser Systems & Solutions of Europe (France) (FR)
- Institute for Microelectronics and Microsystems (IT)
Publication Details
- Journal
- IEEE Transactions on Electron Devices
- Published
- 2025-10-27
- DOI
- https://doi.org/10.1109/ted.2025.3614566
- Primary Topic
- Integrated Circuits and Semiconductor Failure Analysis
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- Centre National de la Recherche Scientifique