Dual-Mode Operated Multilevel Inverter: Design and Hardware Implementation

This work presents a cost effective multilevel inverter topology that caters for dual-mode of operations comprising of symmetrical and unsymmetrical modes. It uses only six switches, two diodes, and two dc voltages sources <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{V}_{1}$</tex>, V 2) to produce five-level output voltage in symmetrical mode <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(i.e.\ \mathrm{V}_{1}=\mathrm{V}_{2})$</tex> and seven-level in asymmetrical mode <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{i}.\mathrm{e}.\ \mathrm{V}_{2}=2\mathrm{V}_{1})$</tex>. A low-cost but quite effective gate driver PC817 is used with each switch, and a low-cost Arduino Uno microcontroller is used for switching signal generation. To ensure high-quality output voltage, switching angles are pre-calculated using low frequency based Half-height modulation scheme. The result shows that the total harmonic distortion (THD) content in the five-level output voltage is 17.67<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">%</sup>, and that for seven-level output voltage is 12.28%. For the switches, the per unit total blocking voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\text{TBV}/\mathrm{V}_{\mathrm{i}\mathrm{n}})$</tex> requirement for symmetrical mode is 10, and that for unsymmetrical mode is 15. The proposed topology is scalable and its feasibility for dual-mode operation is validated using simulation as well as lab scale hardware prototype. All these features confirm the potential of the proposed topology for compact and cheaper solution for multilevel inverter.