20–26-GHz CMOS PA With High <i>P</i> <sub>out</sub> and OP<sub>1 dB</sub> Using a 1:2 Capacitance-Ratio-Equivalent Power Combiner

We demonstrate a four-way wide-band power amplifier (PA1) with a 1:2 capacitance-ratio-equivalent power combiner (PC) and a dynamic-threshold-voltage MOSFET with a resistor (DTMOS-R) using a 90-nm CMOS. Another PA (PA2) without a DTMOS-R using low-loss micro-strip line inductors replaced with a PC is demonstrated for contrast. A low-loss PC is realized using equal <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\lambda $ </tex-math></inline-formula>/4 spiral transmission line inductors based on a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\lambda $ </tex-math></inline-formula>/9 one (with a 1:2 capacitance ratio involving Cp1 and Cp2) for low-loss output-stage matching. The output power of the output stage of PA1, with low-threshold voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm { th}}$ </tex-math></inline-formula>) due to the DTMOS-R and low Rds based on the parallel four-way output, is enhanced using a PC. Between 20–26 GHz, PA1 achieves a prominent S21 of 23.2 dB, peak power-added-efficiency (PAE) between 20.8%–29.7%, and saturation output power between 19.9–21.2 dBm. Moreover, the output 1-dB compression point (OP1dB) is 16–20.4 dBm between 20–26 GHz. Using the PC and DTMOS-R yields the bulk CMOS PA’s high performance (Pout, PAE, and OP1dB), comparable to recent state-of-the-art millimeter-wave PAs, i.e., SOI/SiGe processes.

Authors

Institutions

Publication Details

Journal
IEEE Solid-State Circuits Letters
Published
2025-01-01
DOI
https://doi.org/10.1109/lssc.2025.3529347
Citations
1
Primary Topic
Radio Frequency Integrated Circuit Design
Type
article
Field-Weighted Citation Impact
0.73

Funders

Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

20–26-GHz CMOS PA With High P out and OP1 dB Using a 1:2 Capacitance-Ratio-Equivalent Power Combiner

Jin‐Fa Chang
1 citations
IEEE Solid-State Circuits Letters
Radio Frequency Integrated Circuit Design
0.73
article

20–26-GHz CMOS PA With High P out and OP1 dB Using a 1:2 Capacitance-Ratio-Equivalent Power Combiner

Jin‐Fa Chang
article en
1 citations

Abstract

We demonstrate a four-way wide-band power amplifier (PA1) with a 1:2 capacitance-ratio-equivalent power combiner (PC) and a dynamic-threshold-voltage MOSFET with a resistor (DTMOS-R) using a 90-nm CMOS. Another PA (PA2) without a DTMOS-R using low-loss micro-strip line inductors replaced with a PC is demonstrated for contrast. A low-loss PC is realized using equal <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\lambda $ </tex-math></inline-formula>/4 spiral transmission line inductors based on a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\lambda $ </tex-math></inline-formula>/9 one (with a 1:2 capacitance ratio involving Cp1 and Cp2) for low-loss output-stage matching. The output power of the output stage of PA1, with low-threshold voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm { th}}$ </tex-math></inline-formula>) due to the DTMOS-R and low Rds based on the parallel four-way output, is enhanced using a PC. Between 20–26 GHz, PA1 achieves a prominent S21 of 23.2 dB, peak power-added-efficiency (PAE) between 20.8%–29.7%, and saturation output power between 19.9–21.2 dBm. Moreover, the output 1-dB compression point (OP1dB) is 16–20.4 dBm between 20–26 GHz. Using the PC and DTMOS-R yields the bulk CMOS PA’s high performance (Pout, PAE, and OP1dB), comparable to recent state-of-the-art millimeter-wave PAs, i.e., SOI/SiGe processes.

IEEE Solid-State Circuits LettersVol. 8
National Changhua University of Education (TW)
National Science and Technology Council
Affordable and clean energy
Openalex Percentile: Top 32%
Radio Frequency Integrated Circuit Design
0.73
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.

20–26-GHz CMOS PA With High <i>P</i> <sub>out</sub> and OP<sub>1 dB</sub> Using a 1:2 Capacitance-Ratio-Equivalent Power Combiner — Jin‐Fa Chang · IEEE Solid-State Circuits Letters (2025) | TGRS Research Map | TGRS