Targeted Test Sequence Generation Using the BDD Method to Enhance Assertion-Based Verification Coverage in Simulation

Assertion-Based Verification (ABV) is a powerful methodology used to ensure that designs adhere to specified properties, typically expressed as logical and temporal formulas.Widely regarded as an effective approach to functional verification, ABV dynamically evaluates these properties during simulation.Test sequences are crafted to validate the properties and achieve comprehensive coverage of activation conditions.However, random test generation often leads to insufficient coverage, while exhaustive approaches quickly become impractical as system complexity grows.This article presents an innovative method for automatically generating test sequences using Binary Decision Diagrams (BDDs), ensuring rigorous and efficient verification for critical embedded systems.