A Low-Jitter and Wide-Frequency-Range D-Band Frequency Synthesizer With a Subsampling PLL and a Harmonic-Boosting Frequency Multiplier

This work presents a D-band frequency synthesizer that can generate an ultra-low jitter output signal over a large frequency-tuning range (FTR). To overcome the structural limitations of conventional sub-terahertz (sub-THz) frequency synthesizers and concurrently achieve a low jitter and a large FTR, we designed a two-stage architecture, in which a 50-GHz band subsampling PLL (SSPLL) with a 3rd-harmonic (HM)-rich class-F voltage-controlled oscillator (VCO) in the first stage interoperated with an HM-boosting frequency multiplier (FM) in the second stage. Designed with a 40-nm CMOS process, this D-band frequency synthesizer exhibited a wide FTR of 11.8%, i.e., 144–162 GHz. Due to its high-gain subsampling phase detector (PD), which can suppress in-band phase noise (PN), and its class-F VCO, which can achieve low out-of-band (OOB) PN, the proposed frequency synthesizer achieved the lowest rms jitter (i.e., 39 fs <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{rms}}$</tex-math> </inline-formula> ). Since the combination of the 3rd-HM-rich class-F VCO and the HM-boosting FM generated a D-band output signal in a power–efficient manner, this work also achieved the best jitter figure-of-merit (FOM) among the state-of-the-art W/D-band frequency synthesizers with an FTR more than 5%.