LLM for Complex Signal Processing in FPGA-based Software Defined Radios: A Case Study on FFT

This paper investigates the potential of large language models (LLMs) in accelerating the development of complex signal-processing algorithms on field-programmable gate arrays (FPGAs) for software-defined radio (SDR) systems. Using the Fast Fourier Transform (FFT) algorithm as a case study, we identify two common challenges in applying LLMs to realize intricate wireless communication algorithms on FPGA: 1) handling convoluted mathematical problems and 2) scheduling the execution of sub-modules within the hardware structure. To overcome the first problem, we adapt the chain-of-thought (CoT) prompting technique with a length-limit strategy to enhance the LLM’s Verilog writing performance. To handle the second problem, we develop a novel iterative in-context learning (IICL) prompting scheme that utilizes the iterative structure within the FFT module to perform in-context learning (ICL). These efforts significantly reduce the LLM’s error rate in completing the FFT implementation task and make possible the successful generation of a 64-point FFT module in Verilog, marking a significant milestone as the first LLM-written complex signal-processing algorithm for wireless communication on FPGA.