A High-Speed FPGA Implementation of the Multidimensional Reconciliation for Continuous Variables Quantum Key Distribution

For continuous variable quantum key distribution (CV-QKD) protocol, information reconciliation (IR) is a key step that can significantly affect the performance of CV-QKD. Because of multidimensional reconciliation suitable for low signal-to-noise ratio (SNR) and long transmission distance scenario, a parallel architecture for the multidimensional reconciliation in CV-QKD implemented on field programmable gate array (FPGA) is proposed in this paper. Using a binarized d-dimensional spherical vector c and a parallel computation of the coefficient a and rotation matrix M, the parallel architecture achieves 45.635 Mbps processing throughput at 250 MHz in the system clock, with frame error rate (FER) less than 0.001 when the SNR exceeds 0.71 dB.