Research on Effective Intergrated Circuit Layout Optimization for Edge Computation

The layout of integrated circuits not only has a significant impact on the scalability of the interconnect, the reliability of the chip, the power consumption and delay and other performance indicators, but also has a decisive influence on the subsequent wiring design. First, a diagram-based algorithm is used to preliminarily model the wire mesh of the circuit to determine the possible routing paths. Then, the Deep Reinforcement Learning (DRL) model is used to optimize the prediction of the wiring and component placement of the wire network, and the model learns the best decision according to the local and global layout features. Subsequently, combined with power consumption analysis, the hot spots in the circuit were optimized through the energy-aware clustering method to reduce the overall energy consumption. Finally, the latency and area of the results are evaluated after the layout is completed. Experimental analysis verifies that the proposed method can reduce the layout area and optimize the power consumption while ensuring the performance.