A 50 MHz BW 76.2 dB SNDR CT Modulator for Wireless Receiver

In wireless communication systems, wideband analog-to-digital converters (ADCs) have consistently been a target and hotpots of research breakthroughs. Continuous-time sigma-delta ADCs employ oversampling noise-shaping techniques, along with their inherent anti-aliasing filtering capabilities, to achieve high-precision wideband analog-to-digital conversion, offering advantages in terms of speed, accuracy, and integration. This article presents a continuous-time sigma-delta modulator implemented with a 4th-order, 4-bit quantization feedback architecture, achieving a sampling rate of 2GHz and a signal bandwidth of 50 MHz. By embedding the resonator within the modulator loop, the in-band signal-to-noise ratio (SNR) is improved. Additionally, a two-stage feedforward amplifier structure is designed to achieve higher energy efficiency. Under a supply voltage of 1.2V, simulation results demonstrate that the modulator achieves an SNDR of 76.2 dB, with a modulator loop power consumption of 78.4 mW.