An infrared video image system design based on CameraLink

In order to address the limitations of the CameraLink interface infrared detector on the FPGA side, it was proposed that a wider clock frequency CameraLink decoding read-write display system be implemented. This would help to overcome the challenges posed by factors such as FPGA decoding clock frequency exceeding the generated clock jitter, line field signal instability, signal attenuation, and reflection. The hardware employs a decoding chip to complete the digital video image serial-to-parallel conversion of the CameraLink interface, subsequently outputting the LVCMOS signal. The software utilizes Xilinx IP and custom IP, in conjunction with an AXI4 bus interface, to implement FPGA control logic. Test results substantiate the feasibility of the design, demonstrating that the interface system is in accordance with the provisions of the AXI4 bus protocol, exhibiting high flexibility and application value.