A 0.4-V 13-bit 800-kS/s SAR-ISDM ADC with High-Precision Dual-Bootstrap Switch

This paper presents an analog-to-digital converter (ADC) with a resolution of 13 bits and a sampling rate of 800 kS/s. The ADC utilizes a hybrid structure combining successive-approximation register (SAR) ADCs and incremental sigma-delta modulator (ISDM) architectures for the coarse and fine conversion, leveraging the low power consumption of SAR ADCs and the high precision of ISDM. A high-precision dual-bootstrap switch is proposed, which reduces leakage current by achieving a negative gate voltage. This increases the spurious-free dynamic range (SFDR) of the sampled signal by 7.5 dB and improves the effective number of bits (ENOB) by 1.1 bits. An improved merged capacitor switching (MCS) scheme is presented to avoid using additional reference levels. The hybrid ADC is designed in 14-nm CMOS technology. The simulated SFDR and signal-to-noise and distortion ratio (SNDR) at Nyquist-frequency inputs are 85.52 and 74.54 dB, respectively. The ADC consumes 7.184 μW at 0.4-V supply and 800-kS/s sampling rate. The resultant Walden figure of merit (FoMw) is 2.1 fJ/conversion step.