Fast Energy Optimization of On-Chip ECC Memories

This paper explores the integration of double-error-correcting Bose-Chaudhuri-Hocquenghem (BCH) and single-error-correcting Hamming codes to counter bit-flip errors induced by voltage scaling or radiation upsets in on-chip SRAM modules. Our goal is to optimize the sum of decoding and memory energy, considering that decoder energy is of similar magnitude to memory energy, necessitating precise modeling of the decoder's consumption. We propose accurate models for fast exploration of design space and optimization among many alternative ECC solutions, enabling rapid evaluation of BCH and Hamming decoder energy consumption without circuit synthesis. Experimental results confirm the accuracy of the proposed models. Then, we demonstrate the practical value of these models by utilizing them to identify ECC solutions among a large number of possible code configurations that minimize the total energy consumption of memories subjected to supply voltage scaling or radiation-induced upsets.