Efficient FPGA Implementation of Syndrome-Assisted Layered Belief Propagation Decoder for CV-QKD Systems

In this paper, we propose a QC-LDPC decoder architecture with low complexity as well as excellent decoding performance in CV-QKD systems, which employs the syndrome-assisted layered belief propagation decoding algorithm. To minimize the complexity of hardware implementation and resource consumption in iterative decoding, we use fixed-point numbers instead of floating-point numbers to update node messages. Additionally, two-segment nonuniform lookup tables are employed to implement <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\psi(x)$</tex> efficiently. Besides, the layered syndrome-assisted early termination (LS-ET) scheme is introduced, resulting in the reduction of the number of decoding iterations while maintaining superior frame error rate (FER) performance. The experimental results indicate that the QC-LDPC decoder implemented on an FPGA is capable of achieving throughput of 50.8 Mbps when the code length is 26112 and code rate is 22/68.