Design and Implementation of the High-performance YOLO Accelerator based on Zynq FPGA

YOLO object detection algorithm plays a key role in many application fields. FPGA is suitable for small batch streaming applications with strict power consumption constraints. The current hardware acceleration research generally has insufficient computing power and high difficulty in flexible deployment. This paper is devoted to the design of high-performance and lightweight hardware acceleration system by using software and hardware co-design method. High level synthesis technology is used to design the FPGA hardware to realize the modularization of the operation layer, 16-bit dynamic quantization is used to reduce the size of the model. Convolution expansion and block optimization are exploited to design highly reusable and fluid acceleration circuit, pipeline optimization and multi-channel transmission are used to further reduce the inference delay. In summary, this work implements the accelerators for YOLOv2, YOLOv2-tiny and Improving YOLO three models on ZYNQ FPGA platform. For the accelerator of Improving YOLO, the power consumption is 1.917W, the energy efficiency ratio is 6.23GOP/s/W, and gigabit operations per second is 11.96GOP/s. Comparing with similar works, our work achieves better performance.