Experimental Verification of the Cascade Delay Cancellation in Enhanced Frequency-Locked Loops

Frequency-locked loops are essential elements for the power converters' synchronization as they are used for parameter estimation. However, the fundamental Frequency-Locked Loop structure shows sensitivity to the presence of DC offset and harmonics in the input signal. Those disturbances are causing oscillations in the estimated grid parameters making this technique unusable in those scenarios. The enhanced Frequency-Locked Loop called DC-FLL, solved DC offset sensitivity by introducing a new loop for its estimation and rejection. This paper presents a further modification of the DC-FLL, which is resistant to the presence of harmonics, by applying a Cascade Delay Signal Cancellation. This modification is able to maintain immunity to DC offset, the heritage of the DC-FLL, and also gain immunity to harmonics due to the Cascade Delay Signal Cancellation. To evaluate performance, the experimental setup was prepared and conducted. In the experiment, a few tests were verified by using an acquisition card and the MATLAB/Simulink environment.