Steep Subthreshold Swing Nanoscale Tunnel FET Based on Silicon Tin Channel and High-k Dielectric Gate

In this paper, we introduce an innovative design approach centered on optimized source/channel/drain structure using Silicon-Tin (SiSn) binary alloys to enhance the Subthreshold Swing (SS) factor of nanoscale ultra-thin film Double Gate (DG) Tunnel-FET design. In this context, accurate numerical models taking into account tunneling effects and quantum transport are developed. The influence of the Sn mole fraction on the device's switching characteristics and resulting current capability is thoroughly examined. Additionally, the influence of high-k dielectric materials on device performance is analyzed. The optimized SiSn DG TFET device demonstrates a very low Subthreshold Swing factor of 25.5 mV/dec, while maintaining a reduced ambipolar behavior. Therefore, the proposed design framework strategy paves not only to identify the appropriate binary alloys associated with the optimized mole fraction values, but also to develop efficient ultra-low power multigate transistors.