Experimental Decomposition of the Carrier Mobility in the Conduction Planes of 2-Level Stacked Nanowires

This paper investigates the separation of the drain current components in top-bottom and sidewall currents, and the extraction of their respective low-field mobility in two-level stacked nanowire nMOSFETs. The study presents a detailed analysis of carrier transport in different crystallographic planes, emphasizing the anisotropy in mobility due to variations in sidewall roughness induced by the etching process. Devices with variable fin widths (WFIN) were measured. The effective mobility and the mobility degradation factors were extracted using the Y -function method. This study provides insights into the optimization of process and device modeling for stacked nanowire MOSFETs.