Design of an Approximate Multiplier with Error Recovery and Hardware Optimization

This paper introduces a novel design for an approximate multiplier using an approximate 4-2 compressor, expanding upon conventional approaches. To address errors, it integrates a new error recovery module tailored for minimizing inaccuracies in approximate computations. The error recovery circuit is applied to the approximate compressor, which generates the maximum error. Furthermore, the design employs a truncation technique to simplify hardware complexity. By selectively truncating the lower 4-bits, it achieves a smaller footprint compared to previous models, resulting in reduced hardware complexity and lower power consumption. In essence, the proposed design presents an attractive balance between error recovery, hardware efficiency, delay, and power consumption.